1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor integrated circuit and, more specifically, to a method for adjusting delay time variation caused due to the variation of transistor occurred in manufacturing process.
2. Description of Related Art
In accordance with a demand for a finer structure of CMOS (Complementary Metal Oxide Semiconductor) LSI (Large-Scale Integrated circuit), the variation in sizes of gates (corresponding layout pattern in a mask, after photoresist mask processing (referred to as PR in the following), and after etching (referred to as ET in the following)) on a chip surface tends to affect a transistor characteristic variation within a chip surface. In particular, it tends to become prominent in the 65-nm generation and thereafter.
FIG. 1 shows a structure of a semiconductor integrated circuit described in Japanese Laid-Open Patent Application JP-A-Heisei, 4-247653 as a referential example of a semiconductor integrated circuit. The semiconductor integrated circuit includes a gate circuit 110 having a transistor, a delay time detection circuit 111, and a substrate bias voltage generating circuit 112. The gate circuit 110, the delay time detection circuit 111, and the substrate bias voltage generating circuit 112 are formed on a chip.
The delay time detection circuit 111 detects a delay time between the time where a supply voltage is applied to the gate circuit 110 (a gate of the transistor) and the time where the gate circuit 110 starts an operation (namely, when the transistor is turned ON). The delay time depends on a supply voltage applied to the transistor, environmental temperatures of the transistor, manufacturing processes, and the like. The substrate bias voltage generating circuit 112 generates a substrate bias voltage corresponding to a detected result of the delay time. In this referential example of a semiconductor integrated circuit, the delay time variation caused due to manufacture variation of the gate circuit 110 (the transistor) is adjusted in this manner.